7133SA35JG SRAM Chip Async Dual 5V 32K-Bit 2K x 16 35ns 68-Pin PLCC
From INTEGRATED DEVICE TECHNOLOGY
| Access Time | 35ns |
| Address Bus | 22 b |
| Architecture | Not Required |
| Clock Freq | Not Required MHz |
| Density | 32768 Bit |
| Mounting | Surface Mount |
| Number of Ports | 2 |
| Number of Words | 2K |
| Operating Supply Voltage (Max) | 5.5 V |
| Operating Supply Voltage (Min) | 4.5 V |
| Operating Supply Voltage (Typ) | 5 V |
| Operating Temp Range | 0C to 70C |
| Operating Temperature Classification | Commercial |
| Package Type | PLCC |
| Packaging | Rail/Tube |
| Pin Count | 68 |
| Rad Hardened | No |
| Supply Current | 295mA |
| Sync/Async | Asynchronous |
| Word Size | 16 b |
