F100336QCQR
4-Bit Shift Register

From National Semiconductor

Bits Per Reg.4
Data Inp ModeParallel
Data Outp ModeParallel
MilitaryN
Mode Dyn/ StatStatic
No. of Reg.4
Output Config3-State
P(D) Max.(W) Power Dissipation1.0
PackageQCC-J
Pins28
TechnologyMOS
Vsup Nom.(V) Supply Voltage-5.0
f(oper) Max. (Hz)300M
t(PLH) Maximum (S)3.3n

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