PALCE16V8Q25JC Electrically-Erasable PLD (EEPLD) - Auto reg reset
From Various
| Logic Modes | CombnSeqnt |
| Military | N |
| No. of Outputs | 8 |
| Nom. Supp (V) | 5 |
| Number of Inputs | 16 |
| Output Config | 3-State |
| Package | QCC-J |
| Pins | 20 |
| Prod. Terms Max. | 8 |
| Technology | CMOS |
| t(PLH) Maximum (S) | 25n |
