Datasheet.Directory

{"V(OL)Max.(V)Lo Level Out.Volt.":".33","Digital Input V Max (V)":"7.5","Vsup(+) Nom.(V) Pos.Sup.Volt.":"5","Pins":"N/A","@Iol (A)":"6m","Logic Level Family":"CMOS and T","Package Body Material":"Ceramic","Gate Capacity":"6000","VIL Max. (TTL) (V)":".8","Package":"PGA","VIH Min. (TTL) (V)":"2","@IOH (test)":"6m","Configurable Logic Blocks":"848","Military":"N","Number of User I/Os":"168","V(OH)Min.(V)Hi Level Out.Volt.":"3.84","Vsup (+) Maximum (V)":"7","Technology":"CMOS","Maximum Toggle Rate":"125M"}...

{"V(OL)Max.(V)Lo Level Out.Volt.":".33","Digital Input V Max (V)":"7.5","Vsup(+) Nom.(V) Pos.Sup.Volt.":"5","Pins":"N/A","@Iol (A)":"6m","Logic Level Family":"CMOS and T","Package Body Material":"Ceramic","Gate Capacity":"6000","VIL Max. (TTL) (V)":".8","Package":"PGA","VIH Min. (TTL) (V)":"2","@IOH (test)":"6m","Configurable Logic Blocks":"848","Military":"N","Number of User I/Os":"168","V(OH)Min.(V)Hi Level Out.Volt.":"3.84","Vsup (+) Maximum (V)":"7","Technology":"CMOS","Maximum Toggle Rate":"150M"}...

{"V(OL)Max.(V)Lo Level Out.Volt.":".33","Digital Input V Max (V)":"7.5","Vsup(+) Nom.(V) Pos.Sup.Volt.":"5","Pins":"N/A","@Iol (A)":"6m","Logic Level Family":"CMOS and T","Package Body Material":"Ceramic","Gate Capacity":"6000","VIL Max. (TTL) (V)":".8","Package":"PGA","VIH Min. (TTL) (V)":"2","@IOH (test)":"6m","Configurable Logic Blocks":"848","Military":"N","Number of User I/Os":"168","V(OH)Min.(V)Hi Level Out.Volt.":"3.84","Vsup (+) Maximum (V)":"7","Technology":"CMOS","Maximum Toggle Rate":"200M"}...

{"V(OL)Max.(V)Lo Level Out.Volt.":".33","Digital Input V Max (V)":"7.5","Vsup(+) Nom.(V) Pos.Sup.Volt.":"5","Pins":"N/A","@Iol (A)":"6m","Logic Level Family":"CMOS and T","Package Body Material":"Ceramic","Gate Capacity":"6000","VIL Max. (TTL) (V)":".8","Package":"QFP","VIH Min. (TTL) (V)":"2","@IOH (test)":"6m","Configurable Logic Blocks":"848","Military":"N","Number of User I/Os":"168","V(OH)Min.(V)Hi Level Out.Volt.":"3.84","Vsup (+) Maximum (V)":"7","JEDEC Std 30 Outline Code":"S-CPGA-P","Technology":"C...

{"Status":"ACTIVE","Terminal Finish":"NOT SPECIFIED","Package Body Material":"GLASS","Terminal Form":"WIRE","Diode Capacitance Ratio-Min":"4","Variable Capacitance Diode Classification":"ABRUPT","Package Style":"LONG FORM","Diode Cap Tolerance":"2 %","Diode Element Material":"SILICON","Diode Capacitance-Nom (Cd)":"6.8 pF","Power Dissipation Limit-Max":"0.4000 W","Case Connection":"ISOLATED","Quality Factor-Min":"200","Terminal Position":"AXIAL","Diode Type":"VARIABLE CAPACITANCE DIODE","Package Shape":"ROUN...

{"Category":"Integrated Circuits (ICs)","PCN Obsolescence/ EOL":"Multiple Devices 01/Aug/2014","Number of LABs/CLBs":"848","Mounting Type":"Through Hole","Family":"Embedded - FPGAs (Field Programmable Gate Array)","Number of Logic Elements/Cells":"-","Series":"ACT\u2122 3","Standard Package":"10","Supplier Device Package":"207-CPGA (44.96x44.96)","Datasheets":"ACT 3 Family","Total RAM Bits":"-","Number of Gates":"6000","Operating Temperature":"0\u00b0C ~ 70\u00b0C","Voltage - Supply":"4.5 V ~ 5.5 V","Packag...

{"Category":"Integrated Circuits (ICs)","PCN Obsolescence/ EOL":"Multiple Devices 01/Aug/2014","Number of LABs/CLBs":"848","Mounting Type":"Through Hole","Family":"Embedded - FPGAs (Field Programmable Gate Array)","Number of Logic Elements/Cells":"-","Series":"ACT\u2122 3","Standard Package":"10","Supplier Device Package":"207-CPGA (44.96x44.96)","Datasheets":"ACT 3 Family","Total RAM Bits":"-","Number of Gates":"6000","Operating Temperature":"0\u00b0C ~ 70\u00b0C","Voltage - Supply":"4.5 V ~ 5.5 V","Packag...

{"C1/C2 Min. Capacitance Ratio":"4.3","V(RRM)(V) Rep.Pk.Rev. Voltage":"65","Semiconductor Material":"Silicon","Q Factor Min.":"200","P(D) Max.(W) Power Dissipation":"400m","Package":"DO-7","@Freq. (Hz) (Test Condition)":"100M","Ct{Cj} Nom. (F) Junction Cap.":"6.8p","Military":"N","@V(T){V(J)}(V)(Test Condition)":"4.0"}...